Many systems include a memory circuit for storing application data. Proper operation of the system is dependent on the accuracy of the stored application data. It is known, however, that a memory circuit may store and/or retrieve application data that includes a bit error. For example, a bit error can be introduced in connection with the operation to write application data to a memory. A bit error can also be introduced in connection with the operation to read application data from a memory. It is also possible for a bit error to be introduced during the period of time while the application data is being stored by the memory. To address the concern with such bit errors in the application data, it is known in the art to apply an error correcting code (ECC), also referred to in the art as forward error correction (FEC), to the application data prior to storage. This coding process adds redundant data (for example, in the form of checkbits) to the application data, with both the application data and its associated redundant data being stored in the memory circuit. When later needed, both the application data and its associated redundant data are retrieved from the memory circuit, and the redundant data is used to detect the presence of an error in the retrieved application data as well as, in some instances, correct the detected error.
There is a limit, however, to the number and types of errors that can be corrected for a given ECC. Occurrence of bit errors in excess of that limit can lead to unpredictable results. This could be due to conditions of the operating environment or faults inside the memory circuit. Such unreliable behavior may not be acceptable in some applications. In addition, ECC may not be capable of detecting instances of a memory circuit malfunction.
A specific concern is with a malfunction of the logic circuitry of the memory circuit. Consider the following malfunction relating to addressing: application data with ECC is written to a first memory address within the memory circuit, but because of a malfunction of the logic circuitry within the memory circuit that application data is instead written to a second memory address. This malfunction raises three concerns. First, the data has been stored at the wrong address (i.e., the second memory address). Second, good data at that wrong address has been overwritten. Third, data that should have been overwritten is still present in the memory circuit at the correct address (i.e., the first memory address). Detection of this malfunction in memory operation is critical. However, the ECC does not provide sufficient protection because when a subsequent read from the first memory address is made, the read data versus the ECC will likely reveal no data errors. Similarly, a subsequent read from the second memory address will also likely reveal no data errors.
Consider also the following malfunction relating to chip select: application data is requested by a host for write to a certain selected memory chip, but because of a malfunction in the logic circuitry within the memory circuit for responding to the chip select (CS) signal, no write to the memory occurs. Thus, application data that should have been stored at an address in the memory circuit is not present, and data that should have been overwritten is still present in the memory circuit at that address. Again, detection of this malfunction is critical. However, the ECC does not provide sufficient protection because when a subsequent read from that memory address is made, the read data versus the ECC will likely reveal no data errors.
There is a need in the art to address the detection of malfunctions in memory circuit operation.